#name: Test of SVE2.1 ld1q/st1q instructions.
#as: -march=armv9.4-a
#as: -march=armv8-a+sve2p1
#objdump: -dr

[^:]+:     file format .*


[^:]+:

[^:]+:
.*:	a5902000 	ld1d	{z0.q}, p0/z, \[x0\]
.*:	a5902000 	ld1d	{z0.q}, p0/z, \[x0\]
.*:	a5972000 	ld1d	{z0.q}, p0/z, \[x0, #7, mul vl\]
.*:	a5982000 	ld1d	{z0.q}, p0/z, \[x0, #-8, mul vl\]
.*:	a59f2000 	ld1d	{z0.q}, p0/z, \[x0, #-1, mul vl\]
.*:	a590201f 	ld1d	{z31.q}, p0/z, \[x0\]
.*:	a5903c00 	ld1d	{z0.q}, p7/z, \[x0\]
.*:	a59023c0 	ld1d	{z0.q}, p0/z, \[x30\]
.*:	a59023e0 	ld1d	{z0.q}, p0/z, \[sp\]
.*:	a5808000 	ld1d	{z0.q}, p0/z, \[x0, x0, lsl #3\]
.*:	a580801f 	ld1d	{z31.q}, p0/z, \[x0, x0, lsl #3\]
.*:	a5809c00 	ld1d	{z0.q}, p7/z, \[x0, x0, lsl #3\]
.*:	a58083c0 	ld1d	{z0.q}, p0/z, \[x30, x0, lsl #3\]
.*:	a58083e0 	ld1d	{z0.q}, p0/z, \[sp, x0, lsl #3\]
.*:	a58f8000 	ld1d	{z0.q}, p0/z, \[x0, x15, lsl #3\]
.*:	a59e8000 	ld1d	{z0.q}, p0/z, \[x0, x30, lsl #3\]
.*:	a5102000 	ld1w	{z0.q}, p0/z, \[x0\]
.*:	a5102000 	ld1w	{z0.q}, p0/z, \[x0\]
.*:	a5172000 	ld1w	{z0.q}, p0/z, \[x0, #7, mul vl\]
.*:	a5182000 	ld1w	{z0.q}, p0/z, \[x0, #-8, mul vl\]
.*:	a51f2000 	ld1w	{z0.q}, p0/z, \[x0, #-1, mul vl\]
.*:	a510201f 	ld1w	{z31.q}, p0/z, \[x0\]
.*:	a5103c00 	ld1w	{z0.q}, p7/z, \[x0\]
.*:	a51023c0 	ld1w	{z0.q}, p0/z, \[x30\]
.*:	a51023e0 	ld1w	{z0.q}, p0/z, \[sp\]
.*:	a5008000 	ld1w	{z0.q}, p0/z, \[x0, x0, lsl #2\]
.*:	a500801f 	ld1w	{z31.q}, p0/z, \[x0, x0, lsl #2\]
.*:	a5009c00 	ld1w	{z0.q}, p7/z, \[x0, x0, lsl #2\]
.*:	a50083c0 	ld1w	{z0.q}, p0/z, \[x30, x0, lsl #2\]
.*:	a50083e0 	ld1w	{z0.q}, p0/z, \[sp, x0, lsl #2\]
.*:	a50f8000 	ld1w	{z0.q}, p0/z, \[x0, x15, lsl #2\]
.*:	a51e8000 	ld1w	{z0.q}, p0/z, \[x0, x30, lsl #2\]
.*:	e5c0e000 	st1d	{z0.q}, p0, \[x0\]
.*:	e5c0e000 	st1d	{z0.q}, p0, \[x0\]
.*:	e5c7e000 	st1d	{z0.q}, p0, \[x0, #7, mul vl\]
.*:	e5c8e000 	st1d	{z0.q}, p0, \[x0, #-8, mul vl\]
.*:	e5cfe000 	st1d	{z0.q}, p0, \[x0, #-1, mul vl\]
.*:	e5c0e01f 	st1d	{z31.q}, p0, \[x0\]
.*:	e5c0fc00 	st1d	{z0.q}, p7, \[x0\]
.*:	e5c0e3c0 	st1d	{z0.q}, p0, \[x30\]
.*:	e5c0e3e0 	st1d	{z0.q}, p0, \[sp\]
.*:	e5c04000 	st1d	{z0.q}, p0, \[x0, x0, lsl #3\]
.*:	e5c0401f 	st1d	{z31.q}, p0, \[x0, x0, lsl #3\]
.*:	e5c05c00 	st1d	{z0.q}, p7, \[x0, x0, lsl #3\]
.*:	e5c043c0 	st1d	{z0.q}, p0, \[x30, x0, lsl #3\]
.*:	e5c043e0 	st1d	{z0.q}, p0, \[sp, x0, lsl #3\]
.*:	e5cf4000 	st1d	{z0.q}, p0, \[x0, x15, lsl #3\]
.*:	e5de4000 	st1d	{z0.q}, p0, \[x0, x30, lsl #3\]
.*:	e500e000 	st1w	{z0.q}, p0, \[x0\]
.*:	e500e000 	st1w	{z0.q}, p0, \[x0\]
.*:	e507e000 	st1w	{z0.q}, p0, \[x0, #7, mul vl\]
.*:	e508e000 	st1w	{z0.q}, p0, \[x0, #-8, mul vl\]
.*:	e50fe000 	st1w	{z0.q}, p0, \[x0, #-1, mul vl\]
.*:	e500e01f 	st1w	{z31.q}, p0, \[x0\]
.*:	e500fc00 	st1w	{z0.q}, p7, \[x0\]
.*:	e500e3c0 	st1w	{z0.q}, p0, \[x30\]
.*:	e500e3e0 	st1w	{z0.q}, p0, \[sp\]
.*:	e5004000 	st1w	{z0.q}, p0, \[x0, x0, lsl #2\]
.*:	e500401f 	st1w	{z31.q}, p0, \[x0, x0, lsl #2\]
.*:	e5005c00 	st1w	{z0.q}, p7, \[x0, x0, lsl #2\]
.*:	e50043c0 	st1w	{z0.q}, p0, \[x30, x0, lsl #2\]
.*:	e50043e0 	st1w	{z0.q}, p0, \[sp, x0, lsl #2\]
.*:	e50f4000 	st1w	{z0.q}, p0, \[x0, x15, lsl #2\]
.*:	e51e4000 	st1w	{z0.q}, p0, \[x0, x30, lsl #2\]
